1. Field of the Invention
The present invention relates to a capacitor, and more particularly, to a capacitor used in a semiconductor memory such as dynamic random access memory (DRAM), static random access memory (SRAM), and ferroelectric random access memory (FR).
2. Description of Related Art
Recently, many important parts of computers and communication equipment typically use a large-scale integrated (LSI) circuit having many transistors and resistors that are connected to achieve an electric circuit integrated on one chip. For this reason, the performance of the entire equipment is largely related to the performance of the LSI circuit. The performance of the LSI element can be improved by increasing the degree of integration.
In particular, since DRAM was introduced as a charge-storage solid state memory with a simple structure and manufacturing method in 1970, it has been widely used after increasing its degree of integration. In particular, since 1972, DRAM that includes one memory cell consisting of one capacitor (condenser) and one transistor is used widely due to its simple structure and small size.
In the DRAM, a capacitor comprises a thin dielectric film, such as a SiO.sub.2 system thin film, sandwiched between electrodes, and also stores signal charges. The transistor is used as a switch for identifying and designating the capacitor.
Although the chip area is also slowly increased with the increase in the degree of integration of the DRAM, one memory cell area is decreased at a rate higher than that. Here, the problem is that even if the area of the memory cell is decreased, the electrostatic capacity of the capacitor in the memory cell must be maintained at 30 fF or more in terms of sensitivity of a sense amplifier, the electrostatic capacity of bit lines, and a radiation-resistant soft error.
In order to achieve the correct electrostatic capacity, a first method for thinning a capacitor insulating film (thin dielectric film), a second method for increasing the effective area of the capacitor by making the capacitor structure three dimensional a third method using a dielectric material with a large permittivity, and so forth, are performed. Among these methods, the first and second methods have been mainly adopted until recently.
However, in the first method, the thickness of a SiO.sub.2 film is as thin as 5 nm, and similarly, the thickness of a SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 film, which is a thin dielectric film with a sandwich structure is also as thin as 5 nm. Thus, the leakage current is increased by a tunnel effect, which is problematic.
In the second method, since the three dimensional structure is formed, the process is complicated, so that the number of processes and the step difference are increased. Thereby, the yield is lowered.
In the third method, a high dielectric oxide such as Ta.sub.2 O.sub.5, Y.sub.2 O.sub.3, or SrTiO.sub.3 is used as a high dielectric material; however, since the forbidden band gap is necessarily narrow (3-4 eV) in these high dielectric oxides, the leakage current is also increased.
As mentioned above, along with the degree of integration of the DRAM, the miniaturization of the capacitor for storing signal charges is also in progress. As a result, while the electrostatic capacity of the capacitor is decreased, it is difficult to secure the required electrostatic capacity.
Accordingly, in order to secure the electrostatic capacity, several methods such as thinning of the capacitor insulating film, forming a three dimensional capacitor structure, and adoption of a high-dielectric material were proposed; however, in doing so, the leakage current was increased, or the yield was lowered.